The number of semiconductor memory devices and storage capacity for those memory devices continues to grow, making testing of the memory chips more complex and more expensive. This growth in number and capacity is particularly evident for Dynamic Random Access Memory (DRAM) devices. The variety of DRAM types also continues to grow, supporting a variety of speed grades, storage capacities, and data bit widths. Testing the large capacities and varieties of DRAM memory types becomes even more problematic as data interfaces of 64 bits or more in width appear. Memory testers for such parts will be very expensive. Part of the issue in testing a memory device is that memory die are generally incompletely tested in wafer form. However, when not completely tested before the wafer is separated into individual semiconductor dice, there is the possibility that a memory that passed wafer level tests may fail more rigorous tests later. In areas where bare die are sold for multi-chip modules or three-dimensional packaging, wherein memory devices are stacked, the issues with incompletely tested die will become a greater concern.
At the same time that test issues for individual memory parts continues to grow, the number of memory parts on Dual In-line Memory Modules (DIMMs) and similar carriers continues to increase as does the number and kinds of memory card interfaces. These interfaces often do not easily connect to memory testers for testing the DIMM. As a result, sometimes the DIMMs and memory devices on those DIMMs can only be tested when driven by and incorporated into the processing system for which they are designed. Thus, manufacturing costs and complexity increase and, over time, will become an increasingly important cost factor in the production and maintenance of reliable memory devices.
Furthermore, memory testing often requires detailed testing algorithms that go far beyond simply testing whether a memory cell can retain a “1” value and a “0” value. For example, memory devices may have particular pattern sensitivities based on neighboring data bits within a data word or nearby data words at a different address. In addition, DRAM devices are susceptible to limited data retention times and tests must be devised to verify that data bits will reliably retain their value for a specified period before those values need to be refreshed.
Integrated Built-In Self Test (BIST) capability has been proposed for many types of semiconductor devices, including memory devices. However, often these BIST capabilities are custom designs with little flexibility. In addition, the more flexible designs are large and often include significant requirements for the testing device (e.g., such as a device tester, a memory card tester, or other system devices) to cooperate with the BIST capability.
There is a need for apparatuses and methods to create memory BIST operations that are small and flexible with capabilities to support test operations at wafer level testing, packaged part testing, memory module testing, and system testing.